CWE

Common Weakness Enumeration

A Community-Developed List of Software & Hardware Weakness Types

2021 CWE Most Important Hardware Weaknesses
CWE Top 25 Most Dangerous Weaknesses
>CWE列表> CWE- Individual Dictionary Definition (4.10)
ID

CWE-1280: Access Control Check Implemented After Asset is Accessed

Weakness ID: 1280
抽象:根据
Structure:Simple
View customized information:
+Description
A product's hardware-based access control check occurs after the asset has been accessed.
+Extended Description

该产品实现基于硬件的访问控制检查。仅在支票成功后才能获得资产。但是,如果此操作不是原子,并且在支票完成之前访问资产,则系统的安全性可能会受到损害。

+关系
部分帮助该表显示了与该弱点相关的弱点和高级类别。这些关系定义为childof,parentof,ementof,并深入了解可能存在于较高和较低抽象水平的类似项目。此外,定义了诸如Peerof和Canalsobe之类的关系,以显示用户可能想要探索的类似弱点。
+Relevant to the view "Research Concepts" (CWE-1000)
Nature Type ID Name
ChildOf Pillar支柱 - 弱点是最抽象的弱点类型,代表了与之相关的所有类别/基础/变体弱点的主题。从技术上讲,柱子与类别不同,因为在技术上仍然是一种描述错误的弱点,而类别代表用于分组相关事物的常见特征。 284 Improper Access Control
ChildOf 班级班级 - 以非常抽象的方式描述的弱点,通常与任何特定的语言或技术无关。比支柱弱点更具体,但比基本弱点更一般。班级弱点通常用以下维度的1或2来描述问题:行为,属性和资源。 696 Incorrect Behavior Order
部分帮助该表显示了与该弱点相关的弱点和高级类别。这些关系定义为childof,parentof,ementof,并深入了解可能存在于较高和较低抽象水平的类似项目。此外,定义了诸如Peerof和Canalsobe之类的关系,以显示用户可能想要探索的类似弱点。
+Relevant to the view "Hardware Design" (CWE-1194)
Nature Type ID Name
MemberOf 类别类别- a CWE entry that contains a set of other entries that share a common characteristic. 1198 Privilege Separation and Access Control Issues
+Modes Of Introduction
部分帮助The different Modes of Introduction provide information about how and when this weakness may be introduced. The Phase identifies a point in the life cycle at which introduction may occur, while the Note provides a typical scenario related to introduction during the given phase.
阶段 Note
Implementation
+适用的平台
部分帮助This listing shows possible areas for which the given weakness could appear. These may be for specific named Languages, Operating Systems, Architectures, Paradigms, Technologies, or a class of such platforms. The platform is listed along with how frequently the given weakness appears for that instance.

Languages

Verilog(不确定的患病率)

VHDL(不确定的患病率)

班级:不是特定语言的(不确定的患病率)

Operating Systems

班级: Not OS-Specific(不确定的患病率)

Architectures

班级: Not Architecture-Specific(不确定的患病率)

Technologies

班级: Not Technology-Specific(不确定的患病率)

+Common Consequences
部分帮助This table specifies different individual consequences associated with the weakness. The Scope identifies the application security area that is violated, while the Impact describes the negative technical impact that arises if an adversary succeeds in exploiting this weakness. The Likelihood provides information about how likely the specific consequence is expected to be seen relative to the other consequences in the list. For example, there may be high likelihood that a weakness will be exploited to achieve a certain impact, but a low likelihood that it will be exploited to achieve a different impact.
范围 Impact Likelihood
Access Control
保密
正直

Technical Impact:Modify Memory; Read Memory; Modify Application Data; Read Application Data; Gain Privileges or Assume Identity; Bypass Protection Mechanism

+Demonstrative Examples

Example 1

Assume that the module foo_bar implements a protected register. The register content is the asset. Only transactions made by user id (indicated by signal usr_id) 0x4 are allowed to modify the register contents. The signal grant_access is used to provide access.

(不良代码)
Example Language:Verilog
module foo_bar(data_out, usr_id, data_in, clk, rst_n);
输出reg [7:0] data_out;
输入线[2:0] usr_id;
input wire [7:0] data_in;
输入线clk,rst_n;
电线Grant_access;
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
data_out = 0;
else
data_out =(grant_access)?data_in:data_out;
分配Grant_access =(usr_id == 3'h4)?1'b1:1'b0;
结尾
端模

此代码使用data_out和Grant_access的Verilog阻止分配。因此,这些作业顺序进行(即,首先将data_out更新为新值,而Grant_Access将在下一个周期更新),而不是并行。因此,即使在访问控制检查完成并设置了Grant_Access信号之前,允许对资产数据_OUT进行修改。由于Grant_Access没有重置值,因此它将是元稳定的,并且将随机转到0或1。

Flipping the order of the assignment of data_out and grant_access should solve the problem. The correct snippet of code is shown below.

(good code)
Example Language:Verilog
always @ (posedge clk or negedge rst_n)
begin
if (!rst_n)
data_out = 0;
else
分配Grant_access =(usr_id == 3'h4)?1'b1:1'b0;
data_out =(grant_access)?data_in:data_out;
结尾
端模
+Potential Mitigations

阶段: Implementation

Implement the access control check first. Access should only be given to asset if agent is authorized.
+Content History
+Submissions
Submission Date 提交者 Organization
2020-02-12 Arun Kanuparthi, Hareesh Khattri, Parbati Kumar Manna, Narasimha Kumar V Mangipudi Intel Corporation
+Modifications
Modification Date 修饰符 Organization
2020-08-20 CWE内容团队 MITRE
updated Applicable_Platforms, Demonstrative_Examples, Description, Related_Attack_Patterns
2022-10-13 CWE内容团队 MITRE
更新了示范_examples
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Page Last Updated:January 31, 2023